This invention relates to a semiconductor design and test system for designing and testing semiconductor integrated circuits such as a large scale integrated (LSI) circuit, and more particularly, to an event based semiconductor IC design and test system for testing a semiconductor IC by generating an event based test pattern produced directly from logic simulation data produced in a design stage of the semiconductor IC through a CAD (computer aided design) process.
FIG. 1 is a schematic block diagram showing an example of a semiconductor test system for testing a semiconductor integrated circuit (hereafter may also be referred to as xe2x80x9cIC devicexe2x80x9d, xe2x80x9cLSI under testxe2x80x9d or xe2x80x9cdevice under testxe2x80x9d).
In the example of FIG. 1, a test processor 11 is a dedicated processor provided within the semiconductor test system for controlling the operation of the test system through a tester bus. Based on pattern data from the test processor, a pattern generator 12 provides timing data and waveform data to a timing generator 13 and a wave formatter 14, respectively. A test pattern is produced by the wave formatter 14 with use of the waveform data from the pattern generator 12 and the timing data from the timing generator 13, and is supplied to a device under test (DUT) 19 through a driver 15.
A response signal from the DUT 19 resulted from the test pattern is converted to a logic signal by an analog comparator 16 with reference to a predetermined threshold voltage level. The logic signal is compared with expected value from the pattern generator 12 by a logic comparator 17. The result of the logic comparison is stored in a fail memory 18 corresponding to the address of the DUT 19. The driver 15, the analog comparator 16 and switches (not shown) for changing pins of the device under test are provided in a pin electronics 20.
In a process of developing semiconductor integrated circuits such as a large scale integrated (LSI) circuit, almost always, a design method using a computer aided design (CAD) tool is employed. Such a design environment using a CAD tool is also referred to as an electronic design automation (EDA) environment.
In such a semiconductor development process in an EDA environment, desired semiconductor circuits are created in an LSI with the use of a hardware description language such as VHDL and Verilog. Also in this process, functions of the semiconductor circuits thus designed are evaluated on a computer with use of a software simulator called a device logic simulator.
A device logic simulator includes an interface commonly called a testbench through which test data (vector) is applied to the device design data (device model) showing the intended semiconductor circuits, and the resultant responses of the intended semiconductor circuits are evaluated.
After the design stage of the LSI circuit, actual LSI devices are produced and are tested by a semiconductor test system such as an LSI tester to determine whether the LSI devices perform the intended functions properly. As noted above, an. LSI tester supplies a test pattern (test vector) to an LSI device under test and compares the resultant outputs of the LSI device with expected data to determine pass/fail of the LSI device.
For testing an LSI device which has a higher level of functionality and density, a test pattern to be applied to the LSI device must accordingly be complex and lengthy, resulting in significantly large workloads and work hours in producing the test pattern.
Thus, to improve an overall test efficiency and productivity of the semiconductor integrated circuits, an attempt has been made to use the data produced through the execution of the device logic simulator in an actual test of the semiconductor integrated circuits. This is because the test procedure performed by the LSI tester in testing an actual semiconductor integrated circuit has a substantial similarity with a test procedure by the device logic simulator in testing the design data of the semiconductor circuit in the CAD process noted above.
For example, an attempt is made to produce test patterns and expected value patterns for an LSI tester to test the intended semiconductor integrated circuits by utilizing the data (dump file) resultant from executing the device logic simulation. FIG. 2 is a schematic diagram showing an overall relationship between a design stage of a semiconductor integrated circuit and a test stage of the semiconductor integrated circuit. This example shows a situation where a very large scale integrated circuit (LSI), such as a system-on-chip (SoC) 23 is designed under an electronic design automation (EDA) environment.
After designing the semiconductor integrated circuit 23 under the EDA environment, it is obtained a design data file and a test data file 33. Through various data conversion processes, the design data is converted to physical level data indicating each gate in the designed semiconductor integrated circuit. Based on the physical level data, an actual integrated circuit 29 is produced in a semiconductor integrated circuit production process (silicon process).
The integrated circuit thus produced is tested by a semiconductor test system 30. By executing a logic simulation by a testbench 34 with use of the test data derived through the design stage of the integrated circuit, a data file 35 showing input-output relationships in the integrated circuit is created. An example of such a data file is VCD (Value Change Dump) of Verilog.
As will be described in more detail later, a format conversion process is performed by a conversion software 37 so that the VCD data file 35 described in an event base format is converted to a test signal of a cycle base format. As a consequence, a test pattern in the cycle base is stored in a file 38 in the semiconductor test system 30. A hardware tester 39 applies the test pattern to the device under test 29 for testing the device functions and the like.
As briefly mentioned above, in such logic simulation data, test patterns to be applied to a device model as well as the resultant outputs (expected value patterns) of the device model are expressed by an event base format. Here, the event base data expresses the points of change (events) in a test pattern from logic xe2x80x9c1xe2x80x9d to logic xe2x80x9c0xe2x80x9d or vice versa with reference to the passage of time. Generally, such time passages are expressed by time lengths from a predetermined reference point (absolute time difference) or a time length from a previous event (relative time difference).
In contrast, in an actual LSI tester (semiconductor test system), test patterns are described by a cycle base format. In the cycle base format data, each variable in a test pattern is defined relative to each test cycle (tester rate) of the LSI tester. Thus, as will be explained in more detail later, in a typical LSI tester, a test pattern for a corresponding test cycle is formed based on descriptions of a test cycle (tester rate), waveform (kind of waveform and edge timings), and vector in test pattern data.
As in the foregoing, the existing LSI testers deal with the data in the cycle base while the data produced through the EDA environment is in the event base. Thus, to effectively create test patterns for testing semiconductor devices actually produced based on the CAD data obtained in the design stage of the semiconductor device, it is necessary to convert the event base data to the cycle base data.
Accordingly, in. FIG. 2 noted above, the conversion software 37 extracts the pattern data and timing data from the dump file 35 which is derived from executing the device logic simulation in the design stage of the semiconductor device. The conversion software 37 converts the extracted data to the cycle base data. The pattern data and timing data thus converted to the cycle base format include descriptions regarding the test cycles (tester rate), waveforms (types of waveforms, edge timings), and vectors. The pattern data and timing data are stored in the pattern file 38 in the test system 30.
Based on the data stored in the pattern file 38, the tester 39 which is a cycle based test system generates test patterns to be applied to the DUT 29. As noted above, the test patterns for the existing LSI testers are formatted with use of the test cycle (tester rate) data, waveform (types of waveforms, edge timings) data, and vector data contained in the pattern data and the timing data.
The structure of the cycle based data is shown in FIG. 3. In the example of FIG. 3, the cycle based test patterns are stored in a test pattern file 41 and a test plan file 42. By using the data from these files, an intended test pattern shown in waveforms 45 is formatted by the wave formatter 14 of FIG. 1. Here, the test pattern file 41 stores vector data (also called pattern data) and the test plan file 42 stores the timing data, i.e., the data concerning the test cycles (tester rate) and waveforms (types of waveforms and edge timings).
In FIG. 3, to format the intended waveform 45, vector data such as xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, and xe2x80x9cXxe2x80x9d is set in a pattern description 46, and waveforms and delay data for each test cycle are set in a timing data description 47. The above data need to be defined for each test cycle.
On the other hand, the data produced in the LSI design stage under the EDA environment, such as the data resulted from performing the device logic simulator, has the event based data structure as noted above, which is substantially different from the data structure of the cycle based data of FIG. 3. Such a situation is further explained with reference to FIG. 4. In this example, waveforms 58 in FIG. 4 illustrate the event data from a dump file 57, which is derived from executing the logic simulation, in an event timing sequence. Namely, the event data in the dump file 57 expresses each changing point of the waveforms 58 by a list of set (drive high) and reset (drive low) relative to time.
With reference to FIG. 4, a brief description is made regarding a process of forming the dump file. In designing an LSI under the EDA environment, the designed data is expressed in different levels (hierarchy) of description. In a higher level, more functional description is used, which is converted to lower levels so that in the lowest level, the description in the designed data is in the level of gates of physical structure of the semiconductor device. In FIG. 4, an RTL file 54 stores design data described in a register transfer language (RTL). The RTL design data is converted by conversion software 55 to net list data which is stored in a net list file 56. The net list is a type of data describing the connection relationship among gates which is more closer to the physical structure of the semiconductor device than the RTL design data.
Based on such design data, a testbench 51 provides test vectors to, for example an HDL simulation 52 or a gate level simulation 53 to verify the design data. As a result of the design data evaluation, the dump file noted above is provided with the data describing input events, output events which correspond to the input events, and times of such events.
As in the foregoing, test patterns for testing the designed LSI is created by using the data obtained in the CAD design stage of the LSI, for example, the design evaluation data obtained by executing the device logic simulator produced in the design stage of the LSI devices. However, because such a process involves the test pattern conversion between the different data structures (event base versus cycle base), and further because the functional limitations in the hardware and software of the LSI tester, the event based design evaluation data cannot completely be converted to the cycle based test pattern data.
As a consequence, in testing the semiconductor device with use of the test pattern converted from the design evaluation data, problems in the semiconductor device under test may not always be discovered. In other words, a defect detection rate (debug efficiency) may be decreased. For converting to a more complete test pattern, longer times and heavier workload must be invested, which increases a test cost (overhead) and decreases a test efficiency.
Further, in the conventional semiconductor test system, as in the foregoing, various parameters such as the test cycles, test signal waveforms, timings and logic vectors must be separately described in the pattern data and the timing data. Therefore, to generate the test patterns based on the descriptions separately provided, complicated and expensive hardware and software must be used.
Thus, there is a need in the industry of a high efficiency semiconductor design and evaluation system which can generate test patterns and evaluate the semiconductor device under test, based on the same way of thinking as the evaluation data derived from the EDA environment, and feedback the test result to the EDA environment. It is also desired in the industry to further decrease a time length required for LSI design and its evaluation with use a new semiconductor test system with such a new concept.
Therefore, it is an object of the present invention to provide a semiconductor test system for generating a test pattern by directly using logic simulation data of an LSI device under test or test data in the data structure (event base) similar to the logic simulation data which are formed in the design stage of the LSI under an electronic design automation (EDA) environment and testing the LSI device under test.
It is another object of the present invention to provide an event based semiconductor test system which is capable of producing a test pattern for testing an LSI device under test by directly using the event based simulation data created based on the CAD data derived from the design stage of the intended LSI device under test.
It is a further object of the present invention to provide a semiconductor test system which is capable of producing a test pattern for testing an LSI device under test by directly using the event based simulation data created based on the CAD data derived from the design stage of the intended LSI device under test, thereby substantially reducing a turnaround time between the LSI design and the test pattern formation.
It is a further object of the present invention to provide an event based semiconductor test system which is capable of producing a test pattern for testing an LSI device under test by directly using the event based simulation data created based on the CAD data derived from the design stage of the intended LSI device under test, thereby being able to simplify the software and hardware involved in the semiconductor test system.
It is a further object of the present invention to provide an event based semiconductor test system which is directly related to the EDA research and design environment of the LSI device under test, and which can test the LSI device under test by a test pattern produced directly from the design data, and which can directly feedback the test result to the EDA research and design environment.
It is a further object of the present invention to provide an event based semiconductor test system which is capable of producing a test pattern for testing an LSI device under test by directly using the event based simulation data created based on the CAD data derived from the design stage of the intended LSI device under test, thereby being able to decrease the test cost and increase the test efficiency.
In the semiconductor test system of the present invention, the test pattern is produced by directly using dump file data which is the event based data obtained through executing the device logic simulation on the LSI device designed in the electronic design automation (EDA) environment. The device test is conducted by applying the test pattern thus produced to the LSI device under test, and evaluation of the designed LSI device is feedbacked to the EDA environment based on the test result.
In the semiconductor test system of the present invention, the semiconductor device test is performed with high test efficiency by directly using the data obtained through executing the device logic simulation on the LSI device designed with the aid of computer in the electronic design automation (EDA) environment. The semiconductor test system includes a compiler for converting event data obtained by executing device logic simulation in a design stage of an LSI device under test to an object code; an event file for storing the event data converted by the compiler; an event memory for storing the event data from the event file in two separate types of data, one showing an integer multiple of a reference clock cycle and the other showing fractions of the reference clock cycle; means for generating a test pattern based on the event data from the event memory and applying the test pattern to the LSI device under test; a result data file for evaluating a response output of the LSI device under test and storing resultant evaluation data; and means for evaluating design of the LSI device based on the data stored in the result data file.
As described in the foregoing, in the semiconductor test system of the present invention, the test pattern is produced by directly using the logic simulation data of the device under test obtained in the design stage of the device in the electronic design automation (EDA) environment. The device test is conducted by applying the test pattern thus produced to the device under test. In the semiconductor test system of the present invention, the event based simulation data produced from the CAD design data created in the design stage of the LSI device can be directly used to form the test pattern to test the LSI device.
Thus, according to the semiconductor test system of the present invention, it is possible to significantly reduce the turnaround time from the LSI design to the test pattern production. Further, the test system can be configured by the hardware and software of significantly simple forms. Moreover, since the logic simulation in the design stage of the device and the test pattern applied to the device are structured based on the same basic idea, the test result can be directly feedbacked to the EDA design environment. Further, in the semiconductor test system of the present invention, the device test can be conducted with low test cost and high test efficiency.